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Computer Architecture can assist you in:
writing better programs, writing better compilers, writing better operating systems and designing better computer architectures.
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Changed in the market:
Performance (technology advantages, computer architecture advantages improves low-end), Price (lower cost due to simpler development, higher volumes) Function (Rise of networking/local interconnection technology)
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Moore’s Law:
- number
- of transistors incorporated in a chip will approximately double every 24 months
- (really every 18 months).
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What has increased based on SPEED?
CPU has increase dramatically. Memory and disk have increased only a little
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Dramatic change in technology:
Processor, memory, Disk, and network bandwidth
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The three main computing markets are:
Desktop computing, Servers, Embedded computers
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Quantitative Principles:
Performance, Amdahl’s law, CPU iron equation, dependability
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Execution Time:
Time to run the task (Execution time, response time, latency)
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Performance:
Tasks per day, hour, week, sec, ns (Throughput, bandwidth)
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Response Time (latency):
How long does it take for my job to run, execute, and how long must I wait for the database query.
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Throughput:
How many jobs can the machine run at one, what is the average execution rate, and how much work is getting done.
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If we add a new machine to the lab what do what
do we increase?
Throughput
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Amdahl’s Law:
- · Defines the Speedup
- that can be gained by using a specific feature.
· The performance improvements provided by a feature are limited by how often that feature is used.
· Bottleneck is the most promising target for improvements
· “Make the common case fast”
· Infrequent events, even if they consume a lot of time, will make little difference to performance
· Typical use: Change only one parameter of system, and compute effect of this change. The same program, with the same input data, should run on the machine in both cases.
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“Make the common case fast":
All instructions require an instruction fetch, only a fraction requires a data fetch/store, programs exhibit locality, access to small memories is faster.
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Performance:
NO ONE VARIABLE IS EQUAL TO PERFORMANCE
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Reliability:
The system never fails.
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Availability:
the system can reliably and effectively provide a service
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Combinational circuit:
A digital circuit whose outputs depend solely on the present combination of the circuits inputs’ values
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Sequential circuit:
Output depends not just on present inputs (as in combinational circuit), but on past sequence of inputs. (store bits, also known as having “state”)
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Memory Elements:
Memory elements use in sequential systems are flip-flops and latches.
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Verilog:
Hardware Description Language
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Lexical Conventions in Verilog:
White space and comments:
Free-format language (ignores white space, except where needed to separate language tokens)
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Lexical Conventions in Verilog:
Integer and real numbers:
Express real number in floating-point or scientific notation; Express integer numbers with an optional size and radix.
<size><base format><number>
- 4’b1111
- 12’habc
- -16’d3
- 12’b111_0000_1010
- Real delta = 2.13;
d or D decimal, h or H hexadecimal, b or B binary, O or O octal, X or x don’t care, Z or z high impedance, and _ used for readability
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Lexical Conventions in Verilog:
String constants:
Strings can be stored in reg. The width of the register variables must e=be large enough to hold the string
reg[8*19:1] string_value; string_value = “Hello Verilog World”;
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Lexical Conventions in Verilog:
Identifiers:
- o Can only start with letter or underscore
- o Contain letters, number, $ or underscores
- o Can be up to 1023 characters long
- o Names of instances, modules, nets, ports, and variables are identifiers
- o Verilog is case sensitive
- LEGAL
- Shift_reg1_q
- Busa$index_3
- _bus8
- ILLEGAL
- 34net
- $myreg
- A*3$reg
- n@238
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Lexical Conventions in Verilog:
Specifying Delay:
Use the pound sign (#) character to specify a procedural or primitive delay, you can use this in behavioral statements
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Lexical Conventions in Verilog:
Compiler Directives:
compiler directives direct subsequent compiler interpretation of source code. They remain active from the file that defines them, potentially across other files, to the file that deactivates or overrides them. All compiler directives start with an accent grave (‘), also called a “back-tick”
- ‘define, ‘ifdef, ‘else, ‘endif, ‘inclide, ‘resetall, ‘timescale
- 1ns/1ps, ‘undef
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Verilog Data types:
Nets and Registers:
Nets: represent connections between hardware elements. They are continuously driven by output of connected devices. They are declared using the keyword wire.
Registers: represent data storage elements. They retain value until another value is placed onto them. In Verilog, a register is merely a variable that can hold a value. They do not need a clock as hardware registers do. They can store a signal value across clock cycles.
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Verilog Data types:
Vectors:
A net or register can be declared as vectors, it is possible to address bits or parts of vectors, use integer for counting.
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Verilog Data types:
Reals and Arrays:
- Real: real number
- Array: is possible to have reg, inter, or real
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Memory and Parameter:
Memories: be used to model register files, RAMs and ROMs. Be modeled in Verilog as a one-dimensional array of registers.
Parameter: Define constants and can’t be used as variables.
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Verilog Operator types:
- Operators
- are similar to C except that there are no ++ or --
- · Arithmetic: *, /, +, -, % and **
- · Logical: !, && and ||
- · Relational: >, <, >= and <=
- · Equality: ==, !=, === and !==
- · Bitwise: ~, &, |, ^ and ^~
- · Reduction: &, ~&, |, ~|, ^and^~
- · Shift: <<,>>,>>> and <<<
- · Concatenation: {{}}
- · Conditional: ?:
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Verilog Modeling:
Module:
The internal of each module can be define at four level of abstraction(allows different levels of abstraction to be mixed in the same module)
- o Behavioral or algorithmic level
- o Register-Transfer level
- o Gate level
- o Switch level
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Verilog Modeling:
Ports:
All ports declarations (only: input(right), output(either), inout(bidirectional bus)) are implicitly declared as wire. If the output hold their value, they must be declared are reg
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Verilog Modeling:
Gate level modeling (structural):
All instances are executed concurrently just as in hardware. Instance name is not necessary, the first terminal in the list of terminals is an output and the other terminals are inputs. Not the most interesting modeling technique for our class
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Verilog Modeling:
Initial statements:
An initial block start at time 0, executes exactly once and then never again. If there are multiple initial block, each block starts to execute concurrently at time 0 and each blocks starts execution independently of the others. Multiple behavioral statements must be grouped using begin and end. If there is one statement then grouping is not necessary.
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Verilog Modeling:
Always statement:
the always statement starts at time 0 and executes the statements in the always block continuously in a looping fashion. It models a block of activity that repeated continuously in a digital circuit. Multiple behavioral statements must be grouped using begin and end. If there is one statement then grouping is not necessary.
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Verilog Modeling:
Events-based timing control:
An event is the change in the value on a register or a net. Events can be utilized to trigger the execution of a statement of a block of statements. The @ symbol is used to specify an event control. Statements can be executed on changes in signal value or at a positive (poedge) or negative (negedge) transition or signal.
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Verilog Modeling:
Procedural assignments:
Blocking statements: executed in the order they are specified in sequential block
- a = 14;
- b = 6;
- a = b;
- b = a;
- a = 6;
- b = 6;
Nonblocking statements: executed without blocking the statements that flow in a sequential block
- a = 14;
- b = 6;
- a <= b;
- b <= a;
- a = 6;
- b = 14;
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Mux 4by1
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Logic Synthesis:
Logic synthesis is the process of converting a high level description of design into an optimized gate-level representation. Logic synthesis uses a standard cell library which have simple cells such as basic logic gates like and, or and nor, or macro cells such as adder muxes, memory, and flip-flops. Standard cells put together are called technology library. Normally the technology library is known by the transistor. The impact of HDL and Logic synthesis is that high level design is less prone to human error and is done without significant concern about design constraints.
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Inferring Sequential Elements:
- Sequential elements are the latches and flip flops that make up the storage elements of a register-transfer level system. They are difficult to describe to a synthesis tool. The form of the description of some of these elements (especially flip flops) are almost prescribed so that the synthesis tool will know which library element to map
- the behavior to.
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Latch Inferences:
Latches are level sensitive storage devices. Typically, their behavior is controlled by a system wide clock that is connected to a gate input. Inferred latches are not explicitly specified. To infer a latch two situations must exist that does not assign to an output. (1)At least one control path must exist that does not assign to an output. (2) And the sensitivity list must not contain any edge-sensitive specifications.
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Flip Flops Inferences:
Flip flops are edge-triggered storage devices. Typically, their behavior is controlled by a positive or negative edge that occurs on a special input, called the clock.
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Tips for maintain synthesizability:
- · Avoid %. ** and /
- · Only leaf modules should have functionality
- · Use only positive-edge trigger flip-flops for state
- · DO not assign to the same variable from more than one always block
- · Separate combinational logic from sequential logic
- · Avoid loops like the plague
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