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What does MIPS stand for?
Microprocessor without interlocked pipelined stages
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What does RISC stand for
Reduced instruction set computer
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What is MIPS?
MIPS is a RISC microprocessor architecture
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MIPS data path size
32 or 64 bits
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Load/store instruction set
Before processing data, the data must be copied into registers. The results of the operation must be stored in registers.
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MIPS maximum memory size
230 words
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What does a MIPS memory address point to?
A single byte (byte addressable memory)
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EIU
- Execution integer unit
- Main processor which interprets and executed instructions
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Things included in the EIU
- Registers
- ALU
- Division/Multiplication unit
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The FPU and TMU are both ...
Coprocessors
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TMU
- Trap-memory unit
- Used for interrupts and system control
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Register instruction format
| Field name | Size (bits) |
|---|
| Opcode (op) | 6 | | Source 1 (rs) | 5 | | Source 2 (rt) | 5 | | Destination (rd) | 5 | | Shift amt (often unused, sh) | 5 | | Opcode extension (fn) | 6 |
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Immediate instruction format
| Field name | Size (bits) |
|---|
| Opcode (op) | 6 | | Source or base (rs) | 5 | | Destination or data (rd) | 5 | | Operand/offset | 16 |
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Jump instruction format
| Field name | Size (bits) |
|---|
| Opcode (op) | 6 | | Jump target address | 26 |
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Simple arithmetic/logic MIPS instructions
- add
- sub
- and
- or
- xor
- nor
- All r-type
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Simple immediate arithmetic/logic MIPS instructions
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Instruction format for the j instruction
Immediate
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Instruction format for the jr instruction
Register
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How is the address inferred from the j instruction
- Front: Four bits from program counter
- Middle: 16 Bits from the immediate operand
- Back: Two zeroes (to make multiple of 4)
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Conditional branch instructions
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jr instruction format
- Immediate
- rs holds the address of the register that contains the address to jump to
- op, rt, rd and sh are all 0s
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bltz instruction format
- Immediate
- rs contains address of register to compare
- rt is 0
- Immediate operand is relative branch distance (in words)
- See diagram on chapter 6 notes (part 2)
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bne and beq instruction format
- Immediate
- rs and rt contain addresses of registers to be compared
- Immediate operand is the relative branch distance (in words)
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The addressing modes
- Implied
- Immediate
- Register
- Base
- PC-relative
- Pseudodirect
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Implied addressing
- Location of the operands is predefined
- e.g jal instruction
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Immediate addressing
- Operands are included in the instruction
- e.g addi, andi, ori
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Register addressing
- Operand stored/loaded in/from a specified register
- e.g r-type instructions
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Base addressing
- Operand address is [base register] + [offset]
- e.g lw, sw
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PC-relative addressing
- Instruction address is [offset] + [PC]
- e.g beq, bne
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Pseudodirect addressing
- Address is included in the instruction
- e.g j (jump instruction)
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