1. Characteristic of nMos in Triode/Linear?
    Vgs > Vtn  and Vds< Vgs-Vtn
  2. Characteristic of a nMOS device in cutoff?
    Vgs< Vtn
  3. nMOS  in Saturation has what parameters?
    Vgs> Vtn   and  Vds > =  Vgs-Vtn
  4. What type of signal is less sensitive to noise?
    Digital Signal
  5. MOSFETS can be represented as? 
    nMOS and pMOS
  6. nMOS devices use _______ to carry current.
  7. pMOS devices use _______ to carry current.
  8. A transistor can be thought of as a _______ with states _____ or _______.
    Switch.  On.  Off
  9. DeMorgan's Laws
    —1.   (Barred)  ABC∙∙N=A+B+C+∙∙∙+N

    2.  (Barred)  —A+B+C+∙∙∙N=ABC∙∙∙N
  10. What is positive logic?
    High voltage creates a logic 1 and low voltage creates a logic 0.
  11. What is negative logic?
    High voltages create a logic 0's and low voltages create logic 1's
  12. A circuit's power supply is denoted by?
  13. The switching threshold of the inverter can be denoted as?
    The power supply divided by 2.    (Vdd/2)
  14. —What do we do to the input to have the two switches turn ON and OFF in a complementary manner and still achieve an inverting operation?
    —Insteadof manipulating the input to achieve the inverter operation we can use complementary switches instead.
  15. Ideal switches can be connected in _______ and _______ and represent ______ and ________ operations respectively.
    Series.     Parallel.     AND.      OR.
  16. nMOS are made to pass?
    Logic 0's
  17. pMOS's can pass?
    Logic 1's
  18. Process of constructing an arbitrary
    digital gate is 
    • 1.  Create the pulldown network (PDN) for logic function.
    • 2.—Create the pull-up tree as the dual of the pull-down tree using De Morgan’s Laws.
  19. "A large number of inputs to a gate is required" can also be expressed as?
  20. It is common to have the output of a gate be input to a large number of other gates.  This is called?
  21. An nMOS in cutoff has what characteristics?
    VGS < VThN
  22. An nMOS in the linear/triode region has what characteristics?
    VGS > VThN   &  VDS < VGS - VThN
  23. An nMOS in saturation can be classified by recognizing that these conditions are met.  What are these conditions?
     VGS > VThN    &   VDS >=  VGS - VThN
  24. When VDS = VGS - VThN .  We term can we consider this voltage?
    The edge of saturation (or the "knee")  
  25. A pMOS is in cutoff if ?
    VGS  > VThP
  26. A pMOS device is in the linear/triode region if?
    VGS < VThP        &    VDS > VGS - VThP
  27. A pMOS is in saturation if?
    VGS  <  VThP        &     VDS  <  VGS - VThP
  28. Present day devices’ gate material is made of what material?
    polycrystalline silicon (polysilicon)
  29. How many terminals does the nMOS and pMOS have?
    Four (4)  Gate, Drain, Source, Bulk
  30. What term represents channel length modulation?
    Image Upload 1   (result of pinch off)
  31. Channel length of the transistor is given by:
    • LChannel= Lgate - 2LD
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